Reducing noises of high-speed Bi-JFET charge-sensitive amplifiers during schematic design

Abstract

The technique of circuit noise reduction of charge-sensitive amplifiers containing bipolar and junction field-effect transistors is considered. The initial and improved circuit of the integrated charge-sensitive amplifiers using the above mentioned technique, the results of the step-by-step noise reduction when changing the sizes and operating modes of transistors, and improvement of the bias circuits are presente