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Please use this identifier to cite or link to this item: https://elib.bsu.by/handle/123456789/53836
Title: A switching activity reducing tecnique for the signature analyzer
Authors: Murashko, I.
Yarmolik, V.
Keywords: ЭБ БГУ::ЕСТЕСТВЕННЫЕ И ТОЧНЫЕ НАУКИ::Математика
Issue Date: 2003
Publisher: Минск, БГУ
Abstract: This paper presents new solutions for reducing the power consumption of built-in self-test (BIST) environment such as signature analyzer (SA). The key idea behind this technique is based on the designing a new SA structure for compressing several test responses bits per one clock pulse. The proposed method can be used within "test-per-clock" BIST architecture, as well as may be extended for the "test-per-scan" BIST technique.
URI: http://elib.bsu.by/handle/123456789/53836
Appears in Collections:Chapter 5. ARCHITECTURES FOR IMAGE PROCESSING

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