A switching activity reducing tecnique for the signature analyzer

Abstract

This paper presents new solutions for reducing the power consumption of built-in self-test (BIST) environment such as signature analyzer (SA). The key idea behind this technique is based on the designing a new SA structure for compressing several test responses bits per one clock pulse. The proposed method can be used within "test-per-clock" BIST architecture, as well as may be extended for the "test-per-scan" BIST technique.