Computer-aided inspection of some topological rules of integration circuits layers

Abstract

The visual inspection algorithms for verification of industrial topological rules of integrated circuits are proposed. The algorithms include segmentation of images of topoiogicat layer with subsequent extraction of typical patterns on these images for defects localization. The unique feature of the technology is that the inspection of the design technological rules is performed at different stages of processing. Thus a time-consuming procedure of image matching with the purpose of localization of defects is performed only for some images from the whole image set. The inspection algorithms are included at the system of topological layers processing, which is applied both for topology reconstruction of integrated circuits and for the inspection of its manufacture.