High level programming using a Petry net specification for image processing

Abstract

Configurable computing machines are an emerging class of hybrid architectures where a field programmable gate array (FPGA) component complements the general-purpose microprocessor by enabling a developer to construct application-specific gate-level structures on-demand. Our approach is to provide a very high level Image Processing Coprocessor (IPC) with a core instruction set based on the operations of PRALU. Parallel algorithms are represented in PRALU as a set of linear algorithms that can be executed under the control of mechanism of Petri net type. We describe a high level software environment for FPGA-based image processing from language PRALU. In particular, the focus of this paper is on the hardware compilation part of the problem starting from a software-like algorithmic process-based specification.