H.264/AVC Decoder Prototype Using a Platform Based SoC Design Methodology

Abstract

In this paper, a hardwired solution has been proposed for H.264/AVC decoder based on the evaluation board ML401. The design explored the possibility of achieving both programmability and real-time performance with affordable hardware acceleration. At the same time, features of H.264/AVC processing were analyzed for more suitable accelerator design. The H.264/AVC decoder includes a RISC 32-bits processor Plasma-NTLab and low-cost and reprogrammable accelerators perform computational intensive tasks with high parallelism. The structures of 32-bit RISC processor, syntax parser, NALU decoder, parameters parser and two dimensional DCT have shown in details.